A microcontroller SoC on an open flow
An open-ISA processor core with on-chip memory and standard peripherals taken from architecture through register-transfer design, formal property proof, synthesis, physical design and multi-corner timing sign-off. The engine's contradiction discipline showed up as coverage closure: formal proofs generated the exact stimulus that simulation alone had missed.
⚙ tool-verified Design-flow results re-executed from source; no fabrication claimed. Illustration is symbolic.